On May 20, 5:43*pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> In comp.arch.fpga Mark <m...@cacurry.net> wrote:
> (snip)
>
> <CRC, and LFSR algorithms are the top of the list for implenting in
> < hardware (i.e. HDLs) rather than C. *C implementations are messy.
>
> (snip)
>
> < The core of the verilog code that supports any polynomial
> < (width, taps), and any data size could consist of less than
> < 10 lines of code.
>
> Note that Xilinx FPGAs can do 16 bits of LFSR in one SRL16,
> which takes up very little space. *You could easily generate
> many of them, also wider than 16 bits. *
>
> -- glen

Glen,

That's true. I didn't want the tools to generate FPGA-specific code.

Evgeni