On May 27, 12:37*am, Petter Gustad <newsmailco...@gustad.com> wrote:
> Andreas Ehliar <ehliar-nos...@isy.liu.se> writes:
> > It is straight forward in Verilog as well. This is taken from an Ethernet
> > CRC32 module I wrote a long time ago:
>
> <snipped code>
>
> But that's not any poly at any length...

Andreas's code snippet shows the point fairly well. It's
not hard to expand his to have "polynomial" as an input to
the module as well, and the data length and polynomial length
as parameters.

It's much easier to read his and understand what's happening -
for me at least. Without comments, one can puzzle out the
polynomial, and other CRC parameters fairly easily from the code.
Try that with the machine generated code.

I've inherited machine generated code like these in the past a few
times.
Comments are great, but often get out of date / incomplete / etc.
Next
design, we need to match the CRC in software for some reason. "What's
the polynomial?" the SW engineer asks. "I dunno." HW guy replies,
"So-and-so ran some tool on the net, and out popped this code...".

--Mark