Andreas Ehliar wrote:
> On 2009-05-21, Mike Treseler <mtreseler@gmail.com> wrote:
>> I agree, but not everyone is a language wonk.
>> This is straightforward in vhdl, and has been
>> covered repeatedly in the vhdl newsgroup.
>> If you have done it in verilog,
>> let's see the code.
>
> It is straight forward in Verilog as well.

I agree. But consider what many Verilog designers have learned:

* Think Hardware.
* Don't mix blocking and non-blocking assignments.

If I "think hardware" on an example such as yours, I easily get
confused. To find such an elegant solution, I need to understand
what HDLs and synthesis tools can do.

Likewise, if I can't mix blocking and non-blocking assignments in
a clocked always block, I can't write code like yours.

In summary, unless Verilog RTL designers are prepared to discard
what they are learning from all kinds of papers and trainers,
they won't come up with such elegant solutions. No matter
how straightforward we might find them.

Jan

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