Mark <mark@cacurry.net> writes:

> Ok neat. But why not just code the algorithm in straight verilog or
> VHDL, instead of C generates verilog? The C generated verilog code
> is unmanageable.

I think this historically from the time when synthesis tools did not
handle loops very well. It was very easy to do the expansion
symbolically in a language like Common Lisp and generate HDL code.
I've done this many times in the past and I disagree that the
generated code is unmanageable. You simply stick it in a module and
instantiate it.


Petter
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