Andy wrote:
> Here ya go...
>
> State2 : process(CLK)
> begin
> if rising_edge(CLK) then
> if SINI = '1' then
> State2 <= Idle_S;
> else
> case State2 is
> when Idle_S =>
> if A1 = '1' then
> State2 <= X_S;
> end if;
> when X_S =>
> if A2 = '1' then
> State2 <= Idle_S;
> end if;
> end case;
> end if; -- sini
> end if; -- clk
> end process;

Thanks for taking the time to post this simplified solution.

This thread demonstrates the clarity provided by
minimizing the number of processes in a design entity.
More importantly, it shows the downside of
using an asynchronous process for synthesis.

-- Mike Treseler