On May 26, 5:58*am, Andy <jonesa...@comcast.net> wrote:
> Here ya go...
>
> State2 : process(CLK)
> begin
> * *if rising_edge(CLK) then
> * * * if SINI = '1' then
> * * * * State2 <= Idle_S;
> * * * else
> * * * * case State2 is
> * * * * when Idle_S =>
> * * * * * if A1 = '1' then
> * * * * * * State2 <= X_S;
> * * * * * end if;
> * * * * when X_S =>
> * * * * * if A2 = '1' then
> * * * * * * State2 <= Idle_S;
> * * * * * end if;
> * * * * end case;
> * * * end if; -- sini
> * *end if; -- clk
> end process;
>
> Unless you know that SINI is initially asserted (to initialize the
> state machine), you will need a reset for the state machine too.
>
> Andy

Hi Andy and Brian,
1. Good point: use one process state machine.
2. How do you handle turn-on signals in a state machine?
State2_B : process(State2, A1, A2)
begin
Turn_On <= '0';
case State2 is
when Idle_S =>
if A1 = '1' then
Turn_On <= '1';
State2_NS <= X_S;
-- else <-- key difference
-- State2_NS <= Idle_S;
end if;


when X_S =>
if A2 = '1' then
State2_NS <= Idle_S;
else
State2_NS <= X_S;
end if;
end case;
end process;

3. I don't like one process state machine writing type and Xilinx and
Altera all recommend using 2 process method. I have a state machine
that has 3000 lines and 30 turn-on signals.
One process method is hard to handle my situation.

4. I say VHDL synthesizer should be SMARTER to avoid generating
transparent latch in the exact my situations:
Locally State2_NS is described as transparent latches, but globally,
they are only used in one statement: State2 <= State2_NS; or they are
assigned to registers: State2 which is the case signal in the case
process so that
generating transparent latches for State2_NS is OVER-REACTING and
State2_NS should be generated as a combinational logic !!!

That is what I want to say and highlight !!!

Global optimization rule for VHDL synthesizers: if a type signal (as
State2_NS) is specified in a case process (case process is a process
that contains only one case statement as State2_B shows) as a latch
type, and it is only used to be assigned to the case signal in the
case process, the latch signal can be reduced to combinational logic
without any harm, because the case register keeps the data unchanged
for the latch signal.

Weng