On 2009-05-21, Mike Treseler <mtreseler@gmail.com> wrote:
> I agree, but not everyone is a language wonk.
> This is straightforward in vhdl, and has been
> covered repeatedly in the vhdl newsgroup.
> If you have done it in verilog,
> let's see the code.

It is straight forward in Verilog as well. This is taken from an Ethernet
CRC32 module I wrote a long time ago:

// Ethernet's CRC32
always @(posedge clk125_i) begin
if(crc_enable) begin
crc_tmp = crc;

// Implement it as a for loop of the bit serial version
// and hope that the synthesizer optimize it well (at least ISE does)
for(i = 0; i < 8; i = i + 1) begin
fb = crc_tmp[31];
crc_tmp[31] = crc_tmp[30];
crc_tmp[30] = crc_tmp[29];
crc_tmp[29] = crc_tmp[28];
// ... and so on...
crc_tmp[2] = next_txd_o[i] ^ fb ^ crc_tmp[1]; // x^2
crc_tmp[1] = next_txd_o[i] ^ fb ^ crc_tmp[0]; // x^1
crc_tmp[0] = next_txd_o[i] ^ fb; // 1
end // for (i = 0; i < 8; i = i + 1)

crc <= crc_tmp;
end else if(crc_clear) begin
crc <= 32'hffffffff;
end
end


/Andreas