Hi,
Through discussions of last problem title "Are all these claims in
VHDL correct?" I understand how to recognize a transparent latch from
a register.

Here I gave an example to show what I am puzzled.

State1_A : process(CLK)
begin
if CLK'event and CLK = '1' then
if SINI = '1' then
State1 <= Idle_S;
else
State1 <= State1_NS;
end if;
end if;
end if;

State1_B : process(State1, A1, A2)
begin
case State1 is
when Idle_S =>
if A1 = '1' then
State1_NS <= X_S;
else
State1_NS <= Idle_S;
end if;

when X_S =>
if A2 = '1' then
State1_NS <= Idle_S;
else
State1_NS <= X_S;
end if;
end case;
end process;

State2_A : process(SINI, CLK)
begin
if CLK'event and CLK = '1' then
if SINI = '1' then
State2 <= Idle_S;
else
State2 <= State2_NS;
end if;
end if;
end if;

State2_B : process(State2, A1, A2)
begin
case State2 is
when Idle_S =>
if A1 = '1' then
State2_NS <= X_S;
-- else <-- key difference
-- State2_NS <= Idle_S;
end if;

when X_S =>
if A2 = '1' then
State2_NS <= Idle_S;
else
State2_NS <= X_S;
end if;
end case;
end process;

From my experiences with state machine, VHDL compiler would generate
warning for state2: "state machine state2 will be implemented as
latches".

Once It took me one week to have found the similar situation with the
above state2 in my a long state machine.

I don't know why VHDL compiler generate latches for state2.

Thank you.

Weng