Mark wrote:

> Ok neat. But why not just code the algorithm in straight verilog or
> VHDL, instead of C generates verilog?
....
> You don't need to calculate "one-bit per clock" - rather one-bit per
> ITERATION. Who says each iteration must be a clock tick? Just
> implement the procedural code for the logic update of one bit and
> stick a 'for' loop around it for 'n' bits. Boom, done. Let
> the synthesis tool optimize, and produce the big XOR trees.

I agree, but not everyone is a language wonk.
This is straightforward in vhdl, and has been
covered repeatedly in the vhdl newsgroup.
If you have done it in verilog,
let's see the code.

> The C generated verilog code
> is unmanageable.

http://www.easics.be/webtools/crctool
Is a similar generator that has been around for years.
It produces the same "unmanageable" code that
many have nonetheless managed to
paste in and use successfully


-- Mike Treseler