Evgeni,

Ok neat. But why not just code the algorithm in straight verilog or
VHDL, instead of C generates verilog? The C generated verilog code
is unmanageable.

CRC, and LFSR algorithms are the top of the list for implenting in
hardware (i.e. HDLs) rather than C. C implementations are messy.

You don't need to calculate "one-bit per clock" - rather one-bit per
ITERATION. Who says each iteration must be a clock tick? Just
implement the procedural code for the logic update of one bit and
stick a 'for' loop around it for 'n' bits. Boom, done. Let
the synthesis tool optimize, and produce the big XOR trees.

The core of the verilog code that supports any polynomial
(width, taps), and any data size could consist of less than
10 lines of code.

--Mark