On May 18, 10:14*am, Jake7 <evgen...@gmail.com> wrote:
> I've built a website -http://OutputLogic.com- *with online tools
> that generate a Verilog code for parallel CRC and Scrambler given data
> width and polynomial coefficients.
>
> Also, there are short posts that describe an efficient parallel CRC/
> Scrambler generation algorithm for Verilog or VHDL that I've used.
>
> -evgeni

Thatks for these tools !

How about making it a bit more interesting and adding byte enables ?!

Cheers,
rudi