Hello all

I have made an 8 channel 500kHz low pass IIR-filter in VHDL. The filter uses
32 bits for it's coefficients and 32 bits for it's internal signals.

The filter doesn't give the same DC-gain for small vs. large input signals.
I suspect the internal truncation of the intermediate sums and states
effects this.

But today I thought about increasing the bits for the signal and decreasing
the bits for the coefficients. I tried it out and the filter gave better
gain over different input signal levels.

Now I wonder how I should optimize the coefficient and signal bit lengths to
get the best result?