Franco Tiratore wrote:
....
> I'm currently trying to understand whether or not it is possible to
> implement a 802.11a-compliant OFDM modulator/demodulator on an FPGA.
> As far as I understand, the critical part of the project is the
> 64-point complex FFT with 32 bit floating-point representation (each
> real or complex number is represented in 32-bit floating-point).
> (Do you agree that this is the most critical part? And what about the
> Viterbi decoder?).
> The FFT block should perform this calculation in no more than 2.5 us.

I can't help you out with either FPGAs or OFDM.

But a 64-point complex 32bit floating-point FFT can be executed on a
600 MHZ TigerSHARC TS-201 in about 0.96 us. Perhaps such a DSP is a
viable choice for your project (complex floating-point FFT and Viterbi
decoder are standard library routines, so development time should be at
a minimum).

FWIW,
Andor