"Steve Underwood" <[email protected]> wrote in message
news:[email protected] m...
> "Kevin Neilson" <[email protected]> wrote in message
news:<8oOac.52137$K91.127528@attbi_s02>...
> > > You are sampling two samples per symbol, so if the loop is locked and
you
> > are sampling at the symbol instants and midway between the samples, then
> > x(r-1), x(r-1/2), and x(r) will be three successive samples. These
three
> > would comprise two strobes and one midway or one strobe and two midway
> > samples.
> >
> > The TED can be used to adjust a PLL that controls the sample clock.
Then no
> > interpolation is required; the sample clock is just adjusted so that the
ADC
> > samples at the correct points. That's mostly an older method. The
other
> > type of loop uses an ADC that samples at a constant rate, and then a
> > resampling filter controlled by the loop interpolates the value at the
> > sampling instant, which will be between the ADC samples. Before the
loop is
> > locked, the interpolator will not be sampling at the symbol instants,
but
> > the error value will be large and will push the loop until the
interpolated
> > values occur at the symbol instants and the midway points.
> > -Kevin
>
> Why do you call tuned sampling an older method? It is really a matter
> of circumstances, rather than age. If you are, say, building modems to
> run in the PCM telephone network you have no control over the
> sampling, and have to fiddle things around by filtering. If you have
> control over the sampler, especially for very high speed channels,
> tuning the sampling time to match the symbols simplies things quite a
> bit.
>
> Regards,
> Steve

That was just my observation from what I've seen. In the past, the PLL was
usually external, because it took too many gates to do interpolation of new
samples. I think the trend is to get rid of the analog loop, not because it
is more complex, but because everybody wants to get rid of external analog
parts and suck all that logic into the FPGA/ASIC. It's complex to do the
loop and the Farrow filter interpolation in logic, but gates are cheaper
than VCOs and analaog loop filters. People like to see reference designs
that don't involve a lot of tweaking analog parts.
-Kevin