jdw wrote:

> I plan to be
> a part of this group in the future as I attempt to learn the basics of
> VHDL. Initially it looks more than "Very Hard" DL but what I am
> finding is that part of its difficulty lies simply in becoming
> familiar with the syntax and structure.

My guru on these topics is modelsim.
The error messages are clear and to the point
and the the master is endlessly patient.


-- Mike Treseler