Shannon wrote:
> On Sep 30, 3:21 pm, Jim Lewis <j...@synthworks.com> wrote:
>>> Is there a good reason why VHDL doesnt allow to appear out ports on
>>> right side?
>>> For example:
>>> a <= s1;
>>> This is allowed when s1 is signal and a is out port.
>>> a <= b;
>>> Isnt allowed when b is "out"
>>> Thanks
>> This is fixed in the next revision of VHDL (Accellera VHDL-2006).
>> So if you want this feature, submit a bug report against it.
>>
>> Jim
>
> Fixed? How is it broken? Seems fine to me.

The feature came from ADA. ADA removed the feature
in its 1995 revision.

When you start to write assertions (such as PSL in VHDL
- also a new capability with Accellera VHDL-2006),
you need to be able to read outputs. Sometimes these are
written by Verification engineers who are not permitted
to change the VHDL code.