> Is there a good reason why VHDL doesnt allow to appear out ports on
> right side?
>
> For example:
> a <= s1;
> This is allowed when s1 is signal and a is out port.
>
> a <= b;
> Isnt allowed when b is "out"
>
>
> Thanks

This is fixed in the next revision of VHDL (Accellera VHDL-2006).
So if you want this feature, submit a bug report against it.

Jim