Tricky wrote:

> That is true, but that can make the code harder to read for someone
> else. If you use variables to imply registers or not, then it can be
> hard for someone to work out when or if a register is implied.

Fortunately, synthesis works this out for me.
I verify my work with simulation, not by
synthesizing the code in my head.

Here are some synthesis examples and results
using *no* signals at all.
http://home.comcast.net/~mike_treseler/

> Never
> hold a variable value over a clock edge.

That is strictly a matter of style.
If I followed that rule, it would
be much more difficult for me to
match the algorithms that I need to synthesize.

> I find it best to use variables ONLY for combinational logic and let
> Signals imply the registers.

You are free to use that style.
Many do. But this is not a logical
reason for others be accept such
a limitation.

> It then makes the code easier to read for
> others.

Some others perhaps. Not me.
I prefer reading code with
well-named procedures and functions.

> It also means if you need to access that that register value
> in another process, its always available.

In a single process entity, this is also true.
See my examples.

-Mike Treseler