>
> Just one of the many reasons I like variables: the code "reads" like
> software. The synthesis tool will insert registers (or not) to make
> the hardware behave the same way that the code executes, and the code
> executes the same way that it reads.
>
> Andy

That is true, but that can make the code harder to read for someone
else. If you use variables to imply registers or not, then it can be
hard for someone to work out when or if a register is implied. Never
hold a variable value over a clock edge.

I find it best to use variables ONLY for combinational logic and let
Signals imply the registers. It then makes the code easier to read for
others. It also means if you need to access that that register value
in another process, its always available.