On Sep 24, 8:41 am, Shannon <sgo...@sbcglobal.net> wrote:
> On Sep 24, 1:58 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
>
> > Oh, and you might like to find out about buffer ports, and
> > the VHDL-2002 changes that affect how you can connect buffer
> > and out ports to one another.
>
> And as a beginner that has recently been through all this, I would
> suggest looking into the difference between ports, signals, and
> variables. If 'b' in the above example was a signal for example...all
> would be fine.
>
> Shannon

I suspect you meant to say "if 'b' was a VARIABLE". But it still would
not work... you'd need to change the assignment operator to ":=" too.

Just one of the many reasons I like variables: the code "reads" like
software. The synthesis tool will insert registers (or not) to make
the hardware behave the same way that the code executes, and the code
executes the same way that it reads.

Andy