On Sep 24, 1:58 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> Oh, and you might like to find out about buffer ports, and
> the VHDL-2002 changes that affect how you can connect buffer
> and out ports to one another.

And as a beginner that has recently been through all this, I would
suggest looking into the difference between ports, signals, and
variables. If 'b' in the above example was a signal for example...all
would be fine.

Shannon