Mike Treseler wrote:
> John Smith wrote:
>> Is there a good reason why VHDL doesnt allow to appear out ports on
>> right side?
>
> Yes. The are OUT ports, not IN ports.
>
>> For example:
>> a <= s1;
>> This is allowed when s1 is signal and a is out port.
>> a <= b;
>> Isnt allowed when b is "out"
>
> The OUT port ID goes on the left
> and the value goes on the right.
> The value can be a constant, variable,
> signal, or and expression using these.
> For example:
>
> q <= std_logic_vector(reg_v);
>
> see http://home.comcast.net/~mike_treseler/
> for more examples.
>
> -- Mike Treseler

Yes, maybe somebody can clear what is the reason that OUT ports cannot appear on
the right side.

Thanks for your help.