Binary wrote:

> Can I specify a VHDL file as vector waveform generator in Quartus II
> instead draw a .vwf file, and how?

That would require a vhdl simulator.
Quartus does not have one.

> And how to use a test bench entity to test my entity architecture?

Step one is to install a vhdl simulator
and run some tutorial examples.
A testbench is a vhdl text file.
It includes a null entity and
architecture processes
to wiggle and watch the design instance.
There is a testbench example here:
http://home.comcast.net/~mike_treseler/


-- Mike Treseler