Hi all!
I'm using ISE 6.1 and a Spartan3 fpga. Last day I tried to instantiate a
synchronous FIFO using Logicore.
When I use this instance in my design the beavioural simulation works
perfectly while the post-translate (and the others too) simulation
don't. Looking at the RTL schematic I saw that the vector output of the
instantiated fifo weren't connected with the output and with the other
elements in the design. I tried to instantiate other
memories...asynchronous fifo and so on but the problem is always the
same. What can I do?
The instantiated fifo working in a standalone manner (providing all
signal throug a testbench) work fine even in the post-translate.
Can you help me?
Thanks a lot
Guido

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