The problem is strange.
Our platform is ML555 with Xilinx V5. We need transport data from PC t
DRAM on the board through PCI Express Edge. And we successfully did this o
DELL XPS with nForce 680i motherboard. But when we set up to do it on DEL
t5400 workstation with Intel 5400 we got random errors that the data w
loopback from the SDRAM on the board were wrong and out of order.
I just wondering that which part can produce such errors, PCI Express DM
app or DDR2 Controller? By the way, what we using are all sampl
application provided by Xilinx.

Thanks,
Sam Liu