Hi,

I have read several appnotes about serial interfaces in Xilinx FPGAs.
Most of them use a DCM on the receiving side to phase shift and/or
multiply the incoming clock. My problem is that I don't have any
global clock pins available, only clock capable. So when I use a DCM,
XST gives me an error that I am using a non-optimal IOB site for clock
input. The error can be reduced to a warning be setting a constraint
that allows the non-optimal clock input.

What are the implications of using the non-optimal IOB for clock
input?
Would it be better to try to find a solution that does not include a
DCM in the receiver?