View Single Post
  #5 (permalink)  
Old 11-16-2007, 09:03 PM
Patrick Dubois
Guest
 
Posts: n/a
Default Re: jitter-sensitive multi-output clk distribution formulti-gigabit-transceivers

On 16 nov, 05:15, "Toni Merwec" <mistertorp...@freenet.de> wrote:
>
> I don't think that a regular low-jitter clock device (and it HAS to be
> low-jitter as for the reference for the MGTs) can drive 6 inputs over
> several centimeters. I already used the ICS843020 clock synthesizer in
> several other projects and wanted to use it again. Reason for the ICS is
> that it features a programmable output frequency in the range of 35 - 700
> MHz. Problem is, the ICS843020 has only two outputs. The Epson EG2121CA
> device that is proposed in the Virtex-4 MGT user guide is not suitable
> because these devices are restricted to one fixed frequency.


Check out ICS843001-21:
http://www.xilinx.com/products/board...s843001-21.pdf

It's a frequency synthesizer with very low jitter. It's used on Xilinx
ML505 board for RocketIOs. Then I'm pretty sure that you can find a
low skew clock buffer to drive your 6 clocks.

Patrick
Reply With Quote