"Toni Merwec" <[email protected]> wrote in message
news:473d6db5$0$13113$[email protected]..
>
> I'll be using the Xilinx Virtex-4 FX series FPGAs featuring the high-speed
> MGTs. Unfortunately that leads to a clock signal that has to be
> distributed to at least 6 FPGA clock inputs.
>
> I don't think that a regular low-jitter clock device (and it HAS to be
> low-jitter as for the reference for the MGTs) can drive 6 inputs over
> several centimeters. I already used the ICS843020 clock synthesizer in
> several other projects and wanted to use it again. Reason for the ICS is
> that it features a programmable output frequency in the range of 35 - 700
> MHz.
> Maybe a clock buffer or multi-output clock distribution device is the
> solution here, but I am afraid every additional device in the clock
> network would introduce additional jitter which is the most critical
> aspect in this application. Therefore I woul prefer a solution without
> those kind of devices... if possible.
>
Hi Toni,
A proper clock distribution device will introduce very little jitter. Use
some thing like this:-
http://www.micrel.com/_PDF/HBW/sy89832u.pdf

Filter its supplies properly.

HTH., Syms.