Toni Merwec wrote:
> Has anyone ever had a similar problem and knows about an adequate solution?

I don't know if this meets the jitter precision you need, but we're
using the following setup for 66MHz fpga-fpga communication here:

First FPGA gets an external clock, synchronizes its internal clock to
this via DCM.

Second DCM in first FPGA outputs the clock to a pin, pin is fed back to
another pin that is fed back into DCM-> clock on pin is synchronous to
internal clock.

Second FPGA gets clock from first FPGA, synchronizes its internal clock
to this via DCM.

HTH,

- Philip
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