On Oct 24, 5:04 am, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:
> >For certain addressing patterns, the refresh can be eliminated
> >alltogether, when the addressing sequence is such that all (used)
> >memory cells are naturally being read, and thus refreshed, within the
> >required time.
>
> That happens in a couple of common cases...
>
> Running video refresh out of DRAM
> Running DSP code
> Running memory tests
>
> I once worked on a memory board that worked better (at least as
> measured by memory diagnostics) when the refresh was clipleaded out.
> (We had a bug in the arbiter.)
>
> --
> These are my opinions, not necessarily my employer's. I hate spam.


For SDR SDRAMs, the refresh period depends on the density. Highest
density parts need twice the refresh rate (about 7.8 uS vs 15.6 uS).
If you sensed the part size, or used a DIMM or SO-DIMM with a PROM
for configuration, you may want to set up the refresh rate (once)
after the FPGA is running. A full-fledged SDRAM controller could
also set up other parameters based on a configuration PROM. This
is not something that needs to be dynamic for any given system.
You wouldn't swap out DIMMs with the power on. However it can be
more useful than requiring a different configuration load for the
FPGA depending upon the installed memory.