Special Issue of Journal of Scalable Computing: Practice and
Experience High Performance Reconfigurable Computing (HPRC)


High Performance Reconfigurable Computing (HPRC) has become a crucial
research tool in order to design application-specific processors/cores
in
a number of domains such as digital signal processing, robotics,
graphics, cryptography, and bioinformatics, to name just a few.
Better languages and tools especially designed for HPRC as well as
novel architectures of HPRC devices and systems are required more and
more.
Furthermore, algorithms, methodology and best practices for obtaining
HPRC designs are still in-progress research problems.


Papers are solicited in topics related to high performance
reconfigurable
computing, including but not limited to


* Applications in science and engineering.


* Architectures of HPRC devices and systems.


* Languages and tools for HPRC


* Algorithms, methodology and best practices for HPRC


* Performance and benchmarks


Authors are invited to submit full papers electronically in English,
in PDF format, with a maximum length of 15 pages to one of the
following
guest editors:


Dorothy Bollman (bollman(at)cs.uprm.edu)
Department of Mathematical Sciences
University of Puerto Rico at Mayaguez


Javier Diaz (jdiaz(at)atc.ugr.es)
Department of Computer Architecture and Technology
University of Granada


Francisco Rodriguez-Henriquez (francisco(at)cs.cinvestav.mx)
Center for Research and Advanced Study
National Polytechnical Institute, Mexico


Submitted articles must not have been previously published or
currently
submitted for journal publication elsewhere. Papers will be peer-
reviewed by at
least two external reviewers. Authors of accepted papers will be
required to
prepare the text in LaTeX using SIAM journal style (see http://www.scpe.org).


Please note the following important Dates:
submission deadline October 8, 2007
author notification December 5, 2007
camera ready submission January 7, 2008
publication March, 2008