"Gabor" <[email protected]> wrote in message
news:[email protected] ups.com...

>>Just out of curiosity, whay would you want to add delays
>>from the master?

I don't want the master to explicitly add delays. I'm
rewriting the i2c master module and i get caught by
the same question again "What if the user module of
the i2c core didn't provide the next data fast enough?
(i also considered a fifo). I know that 100/400Khz are
slow enough compared to the user mode clk speed, but i
believe in black boxes or what object oriented approaches
call incapsulation. The user module doesn't have to depend
on its child module implementation when possible and
viceversa. So i'm figuring out whether i can make the core
robust such that it can recover in cases of delayed data
arrival. That said, even with a robust core the user module
will implement things such that delays don't happen.


see you, Gabor