devices wrote:

> "John_H" <[email protected]> wrote in message
> news:[email protected]..
>
>
>>>>>>>>>As for the I2C Master, assuming no clock stretching
>>>>>>>>>is issued by the Slave,
>
>
>>This is a bad assumption. The common situations that include delays must
>>have the SCL clock stretching from the slave. Without that clock
>>stretching, there's no idea when b1 or b2 start. The SCL holdoff is
>>explicitly to allow for slave latency.
>
>
> For the sake of generality, the clock stretching not only applies
> to a byte level, it also applies to a bit level. Fortunately common
> situations are not general situations or it would mean that every
> i2c slave device would be always slower with respect to its
> specifications. So i can always take into account the latency as
> a preliminary step. But what i was investigating on was the possibility
> of the master to introduce a delay.

Clock stretching is a means whereby a Slave tells the master to
'pause' - it has no real meaning in a Master context.
To any slave, it is just a wider SCL pulse, and slaves only have a min
time spec [unless you also have lock-out watchdogs, but they are rare]

Even Slave Clock stretching is rare. It is in the spec, but not often
used. i2c speeds are very slow by modern silicon standards, so
slow-down-more is not often a problem !

Serial EE proms, have chosen a polling system for their 'wait'
requirements.


-jg