"Mike Lewis" <[email protected]> wrote in message
news:c2ac4$46a4c534$401a86c3$[email protected]..
>
>
> "devices" <me@home> wrote in message
> news:46a4bbc3$0$37203$[email protected] ...
> > As for the I2C Master, assuming no clock stretching
> > is issued by the Slave, here is a common situation and
> > its concerning counterparts.
> >
> > Usual scenario:
> >
> > 1) Start - b1 - b2 - Stop
> >
> > And relative CONCERNING scenarios:
> >
> > 2) Start - b1 - DELAY - b2 - Stop
> > 3) Start - b1 - b2 - DELAY - Stop
> >
> > (and why not) Start - DELAY - b1 - b2 - Stop
> >
> > Where:
> >
> > b1 is a completely transferred and acked byte
> > b2 as above
> > DELAY is at least, more than a single SCL period.
> >
> > The difference between 1 and 2, 3 is the DELAY.
> > Is such a delay allowed? If it is, which is the
> > polarity of SCL when the master is (let's say)
> > "stretching"? Low? (i'm not considering a multi-master
> > bus)
> >
> >
> >
> >
>
> SCL is usually an open collector style of signal. As such it can only be
> driven low (floated high). So that means, if the slave is inserting the
> DELAY it will drive
> SCL low for the duration of the DELAY.
>
> I believe a DELAY could occur for any of the scenerios that you mentioned.
>
> If the master is inserting the DELAY (you have a single master system) ...
> it doesn't matter what the state of SCL is as long as it doesn't toggle
and
> provide a rising edge.
>
> Mike
>

Mike, thanks.