As for the I2C Master, assuming no clock stretching
is issued by the Slave, here is a common situation and
its concerning counterparts.

Usual scenario:

1) Start - b1 - b2 - Stop

And relative CONCERNING scenarios:

2) Start - b1 - DELAY - b2 - Stop
3) Start - b1 - b2 - DELAY - Stop

(and why not) Start - DELAY - b1 - b2 - Stop

Where:

b1 is a completely transferred and acked byte
b2 as above
DELAY is at least, more than a single SCL period.

The difference between 1 and 2, 3 is the DELAY.
Is such a delay allowed? If it is, which is the
polarity of SCL when the master is (let's say)
"stretching"? Low? (i'm not considering a multi-master
bus)