[email protected] wrote:
> I am trying to synthesize a code using ISE which contains a component
> fifo the fifo code is the following
>
> -- synopsys translate_off
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> library UNISIM;
> use UNISIM.VCOMPONENTS.ALL;
> use UNISIM.VPKG.ALL;

Don't use VPKG, and put the translate_off/on only around the unisim
stuff (in this case "synthesis" is a synonym for "synopsys"):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- synthesis translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synthesis translate_on