Marco,

The way to do this is to use the TMR Tool(tm), which triplicates
everything, including resets, clock trees, etc. including triple voting
of all feedback paths.

The tool automatically takes a design, and creates a functionally
correct triplicated version.

Nothing will prevent soft errors (exept being 30 meters underwater).

In addition to TMR, the device also requires scrubbing, or frame error
correction (available on V4 and V5). That way a bit flip is corrected
before another one happens.

http://www.xilinx.com/support/traini...s/tmr-tool.htm


Austin


Marco T. wrote:
> Hallo,
> I should develop a safety-critical application using Xilinx fpga.
> The system should be immune from matrix interconnect switch changes
> (soft-errors) during operation, otherwise, if a switch changes the
> interconnection, it should go into a safe state.
>
> There is a way to implement fail safe interconnections (pip), in example
> setting some parameters using PAR?
>
> I already read the manual, but I don't have found such information. There
> lots of parameters about timing, but it's not clear about safe
> implementation.
>
> I read also about scrubbing and readback, but I was wondering if PAR could
> be able to do it.
>
> It is possble to know how PAR works at low level, or it's secred and covered
> by patents?
>
>
> Many Thanks
> Marco T.
>
>