I generated a fifo with block rams with two independent clocks and a
symmetric widths and depths. the fifo manual digrams state that with
read enable high the data can be read out of the fifo every clock
cycle.
The wr_en signal is running at a half of the write cycle frequency .i.e
the valid data is present on the input bus every second cycle of write
clock. Now once the data has been written I disable the wr_en . I
enable the read enable and the signal is kept at constant high till the
fifo becomes empty.
I simulated the fifo and it turns out that the fifo ouputs the data
every second cycle with a constant high on the rd_en pin.

Is there something to be tweaked to make it output every clock cycle or
is that the peak performance?