Ndf wrote:
> Hello,
>
> For a low power application I would like to stop the clock feed into a FPGA
> when enter "sleep mode". This is a common practice or can be dangerous? And
> if is dangerous why? Maybe a silly question but I want to be sure about
> that! I use Lattice XP parts.
>
>
>
> Thanks,
>
> Dan.

Some things to consider:

How do you exit "sleep mode"?

Does this require the clock you're stopping?

If so does the clock signal still exist in a portion of the design?

Were you considering using the FPGA to stop its own clock or
use an external component? It may not be easy to stop the clock
internally if you need to meet a certain phase relationship with
external parts. Normally gating off a global clock will require
adding some logic between the clock input pin and the global
buffer (this would not be the case for parts with dynamic clock
select resources, such as EC/ECP - I'm not sure if XP has these).
It may be possible to fix phase problems with a PLL, but again
if you stop the input to the PLL you'll need to reset it when you
start the clock again. DLL's have similar issues. Also if you use
either of these, you'll have problems if you need to come up
operational within a few clock cycles of exiting "sleep mode".

Good Luck,
Gabor