Hi Austin,
besides everything concerning the security gain of an encrypted
bitstream I have a different question.

Xilinx offers a similar feature too in its Virtex4 (and 5?) FPGAs.
Now, that some silicon already is used up by the AES algorithm, wouldn't
it be nice to make it accessible to the custumer? Just the Keyscheduler
and the round function, not the key memory.

Would be a nice feature for some custumers, but (nearly) no drawback for
all others.

Best regards
Eilert