Marco

How many layers you end up using depends a lot on the manufacturer that
you use for pcbs and their technology abilities, (principally track and
gap and via size etc), that you use. I would say using the FT256 that a
4 layer board is easily viable on the right technology level probably
4/5 thou (0.1-0.127mm) track and gap and maybe down to the easier 6
thou or 0.15mm track and gap. A 6 layer board will probably allow you
to use 8 thou or 0.2mm track and gap and allow a wider choice of
potential pcb manufacturers. How you do it wil vary a lot depending on
your pcb layout and what things connect to and where i.e. where things
are placed but to give you a practical example of what can be achieved
is our low cost Raggedstone1 product that achieves a full use of
XC3S400(264 I/O), in a FG456 package, on a 4 layer board. I will say
that wasn't easy even by our standards. The comparitive product of
Xilinx(Digilent) Spartan-3E Starter Kit board I believe has 8 layers to
do less than we do with I/O.

On a more general point Xilinx used to have breakout patterns for
things like Virtex2. Do have a search for those on their site. The is
also some useful info here
http://www.xilinx.com/bvdocs/userguides/ug072.pdf.

John Adair
Enterpoint Ltd.

Marco wrote:
> Hi all,
> as many of you may know after all my posts, I'm working with a Spartan3
> in the FT256 BGA package. Could anyone give me a link or something on
> documentation that may help me routing all those pins out in that kind
> of package with a 4-6 layer board. I'd like to get some examples or
> guidelines related to the most common approach adopted by experienced
> people.
> Thanks,
> Marco