Marco,
try this
http://www.xilinx.com/bvdocs/appnotes/xapp157.pdf
Aurash


Marco wrote:

>Hi all,
>as many of you may know after all my posts, I'm working with a Spartan3
>in the FT256 BGA package. Could anyone give me a link or something on
>documentation that may help me routing all those pins out in that kind
>of package with a 4-6 layer board. I'd like to get some examples or
>guidelines related to the most common approach adopted by experienced
>people.
>Thanks,
>Marco
>
>
>


--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/

phone: 353 01 4032639
fax: 353 01 4640324