Franco Tiratore wrote:

> Hi all.
>
> I'm currently trying to understand whether or not it is possible to
> implement a 802.11a-compliant OFDM modulator/demodulator on an FPGA.
> As far as I understand, the critical part of the project is the
> 64-point complex FFT with 32 bit floating-point representation (each
> real or complex number is represented in 32-bit floating-point). The
> FFT block should perform this calculation in no more than 2.5 us.
> I'm not an expert in this field, can anyone help me to understand
> whether or not this performance is achievable with the FPGAs currently
> available on the market? If yes: can you address me to some specific
> FPGA model? If not: what is the critical part of my specifications? (I
> suppose the time delay and the floating point spec).
>
> This is only one of my current doubts.
> I hope we can start a profitable discussion. :-)
>
> Ciao,
> Franco
>

Pretty much any of the current FPGA offerings are capable of 64 point
FFTs in 2.5 us. For OFDM, there really isn't any need to use floating
point. Floating point trades accuracy for dynamic range. In the case
of OFDM, you have 64 point FFT, so at most you'll have a growth of 6
bits in your data. Presumably, the data is coming from a DAC through
some filters, so the dynamic range of the data coming into the FFT is
also not that large. A single precision floating point FFt is going to
have a 24 bit data path plus an 8 bit exponent. A 24 bit fixed point
data path with no exponents is more than enough for this application.

There are FFT cores in the cores offered by the major FPGA vendors.
These are not bad considering the price (free). You can obtain
considerably higher performance and smaller size from third party IP
providers, but it is not free.

In any event, you need to look at the entire OFDM receiver, as the FFT
is only one block of it, and can be readily found off-the-shelf.