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Old 05-11-2006, 09:55 AM
Franco Tiratore
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Default Re: 64-point complex FFT with 32 bit floating-point representation

dal ha scritto:

> Franco Tiratore wrote:
> > I'm currently trying to understand whether or not it is possible to
> > implement a 802.11a-compliant OFDM modulator/demodulator on an FPGA.

>
> Yes it is possible, you need to choose an FPGA large enough.



Wonderful!


> The FFT is relatively easy, using fixed-point arithmetic. No reason to
> use floating point.



Can you explain this to me? This is a critical point!
I had a look at a master thesis of a guy here at the university...
He wrote that a floating point representation is required (but he
didn't write why).
It would be much easier to operate with fixed-point numbers, but I
should understand why...


> Other parts of the system are more challenging.



Do you mean the Viterbi decoder?


> > FFT block should perform this calculation in no more than 2.5 us.

>
> Easily achievable without requiring a high clock rate.



I think you mean with fixed-point numbers...


> The first thing you need to do is come up with an outline design for the
> complete implementation, not just the FFT. Then estimate the size of
> each block, and the total size of the design. Do this before you select
> the FPGA, and work out what clock rate is required and how much memory
> you need.
>
> You can break each part of the design into small blocks and learn as you
> go. Start with the FFT if you want, but it will not be the most
> difficult part. There are many papers on different FFT architectures,
> google for 'r2sdf fft' for examples.



Thank you for your suggestions!
The problem is that my boss told me:
"Ok, we want to have an FPGA implementation of an 802.11a modem.
Before starting with VHDL, we need to understand which are the critical
blocks and find an appropriate FPGA for our project.
You have 1 week for this task."
We will have a meeting during the next days, I will explain him the
approach you suggested me.

Ciao,
Franco.

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