Franco Tiratore wrote:
> Hi all.
>
> I'm currently trying to understand whether or not it is possible to
> implement a 802.11a-compliant OFDM modulator/demodulator on an FPGA.

Yes it is possible, you need to choose an FPGA large enough.

> As far as I understand, the critical part of the project is the
> 64-point complex FFT with 32 bit floating-point representation (each
> real or complex number is represented in 32-bit floating-point). The

The FFT is relatively easy, using fixed-point arithmetic. No reason to
use floating point. Other parts of the system are more challenging.

> FFT block should perform this calculation in no more than 2.5 us.

Easily achievable without requiring a high clock rate.

> I'm not an expert in this field, can anyone help me to understand
> whether or not this performance is achievable with the FPGAs currently
> available on the market? If yes: can you address me to some specific
> FPGA model? If not: what is the critical part of my specifications? (I
> suppose the time delay and the floating point spec).
>

The first thing you need to do is come up with an outline design for the
complete implementation, not just the FFT. Then estimate the size of
each block, and the total size of the design. Do this before you select
the FPGA, and work out what clock rate is required and how much memory
you need.

You can break each part of the design into small blocks and learn as you
go. Start with the FFT if you want, but it will not be the most
difficult part. There are many papers on different FFT architectures,
google for 'r2sdf fft' for examples.