Hi all.

I'm currently trying to understand whether or not it is possible to
implement a 802.11a-compliant OFDM modulator/demodulator on an FPGA.
As far as I understand, the critical part of the project is the
64-point complex FFT with 32 bit floating-point representation (each
real or complex number is represented in 32-bit floating-point). The
FFT block should perform this calculation in no more than 2.5 us.
I'm not an expert in this field, can anyone help me to understand
whether or not this performance is achievable with the FPGAs currently
available on the market? If yes: can you address me to some specific
FPGA model? If not: what is the critical part of my specifications? (I
suppose the time delay and the floating point spec).

This is only one of my current doubts.
I hope we can start a profitable discussion. :-)

Ciao,
Franco