Vladislav Muravin wrote:
> Why not designing a FIFO on your own?
>
> V
>

Yeah, that's what we're doing now.

It is just that when they give you the freebie library of components
why re-invent the wheel, right?

Of course, their %#$%$%$^@# component doesn't work for crap, so they
basically steer you down a dark alley for a day or so.
We had it integrated in a DMA mechanism and when stuff doesn't work,
you don't immediately assume it is the commercially availbable
component -- one would hope they test their junk before it is thrown
over the wall (I guess they didn't).
So the first thing you assume is bad is your own code..

I guess you get what you pay for.

Remco


>

> "Remco" <[email protected]> wrote in message
> news:[email protected] ups.com...
> > Hi all
> > We've set up a simple FIFO on a Spartan3 FPGA using the free code from
> > Xilinx XApp258 (FifoCTLR_IC_V2.vhd)
> > Initially this mechanism was tied to a DMA and we were having a hard
> > time figuring out what was going on.
> > By process of elimination, we tied the FIFO to an address and used the
> > read/write strobed to read and write to the fifo.
> >
> > We can scribble data and read it back.
> > The weird thing we're seeing is that the "empty" does not become true
> > until data is read for the first time. It also becomes untrue with data
> > left in the FIFO (usually 2 longs remaining).
> >
> > Has anyone seen this before? Or do we need to pay for the libary to get
> > it fixed
> >
> > TIA
> > Remco
> >