"Remco" <[email protected]> wrote in message
news:[email protected] ups.com...
> Hi all
> We've set up a simple FIFO on a Spartan3 FPGA using the free code from
> Xilinx XApp258 (FifoCTLR_IC_V2.vhd)
> Initially this mechanism was tied to a DMA and we were having a hard
> time figuring out what was going on.
> By process of elimination, we tied the FIFO to an address and used the
> read/write strobed to read and write to the fifo.
>
> We can scribble data and read it back.
> The weird thing we're seeing is that the "empty" does not become true
> until data is read for the first time. It also becomes untrue with data
> left in the FIFO (usually 2 longs remaining).
>
> Has anyone seen this before? Or do we need to pay for the libary to get
> it fixed
>
> TIA
> Remco

Or you could use the Xilinx FIFO Generator v2.2 Logicore for a more fully
specified interface. The user guide has timing diagrams and signal
descriptions that are probably much better than the XAPP258.