>yeah, if one has patience, one can derive each byte one by one.
>I thought there must be some shortcut to this tideous process.

Are you trying to understand how it works or looking for a
simple recipe for getting the job done?

I don't know of a simple recipe. I think there was a web
site that may have generated VHDL/Verilog for CRCs. I forget.
It was a long time ago. It might have done the parallel mode.

The software guys often do CRC calculations a byte at a time
rather than a bit at a time. You can probably find a lot
of good info via google. Basically, it involves a table
lookup. The length of the table is the size of your "byte".
The width of the table is the width of the polynomial used
to make your CRC. To do the normal CRC-32 (Ethernet) CRC
a byte at a time takes a 256 entry table where each entry
is 4 bytes wide.

You can implement that table in hardware with a cloud of XOR
gates. Some of the software routines compute the table
at initialization time rather than pre-computing it and
feeding a table of constants to the compiler. That tells you
the cloud of gates that you need. (I think.)

There are many ways to screwup CRC/scrambler calculations.
The common ones are getting left/right mixed up. I strongly
suggest checking things ahead of time with software/simulations.

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