newsgroup wrote:
> Kris,
>
> definitely yo can do the whole process in one go.
> For that either you have to write a simple program which tells you the bit
> combinations or
> since in your case, data is just 8 bits, so you can manually derive the
> equation
>
> But I guess, the synthesis tool will be doing the same thing for you, if you
> just write everything in loop, can't guarantee but it should do so.....

Yes, it works. I have made scramblers that way (in VHDL). It should
also be possible in Verilog, assuming your tool implements the 2001
version of the language.

Regards,
Allan